extensive verification

英 [ɪkˈstensɪv ˌvɛrɪfɪˈkeɪʃən]

美 [ɪkˈstensɪv ˌvɛrəfəˈkeɪʃən]

广泛的核实

Both said Friday they had extensive discussions on verification issues but did not indicate they had reached a final agreement.
双方星期五都表示在核项目确认问题上进行了深入讨论，但并没有说他们达成了最终协议。
As a result, stacks that claim to support a particular standard rarely do any extensive verification of their support.
结果声明支持特定标准的栈很少验证它们的支持。
Verilog-HDL is one of the most extensive hardware description languages ( HDL). It fits for both the design and the description of each level of algorithm, gate to switch and simulation verification, sequence analysis etc.
Verilog-HDL是应用最为广泛的硬件描述语言（HDL）之一，它适合于从算法级、门级到开关级的各个层次的设计和描述，也可以进行仿真验证、时序分析等。
Finally, Experimental conclusion is verified by ANSYS with reasonable model and parametric selection, and an extensive parametric analysis is performed finally based on the verification.
最后，通过合理的参数选取和模型设置，利用ANSYS软件对试件的试验结果进行有效验证，并在此基础上进行了扩大参数分析。